Cool ways to cut chip power drain

Multicore processors have allowed Intel to boost processing speed without increasing clock frequencies, power consumption and cooling requirements. In addition, entire cores can be switched off to conserve power when not needed; and processing can be circulated around the cores to avoid hotspots.

But, as chief executive Paul Otellini pointed out , major changes to the core architecture are needed to produce the tenfold reduction in power drain envisaged by Intel.

One approach is to use new materials to reduce both unwanted leakage currents and the charge required to switch on a transistor.

Another is to use two types of transistor, one fast with high leakage and the other slower but less power hungry, and use the former only when needed, Intel technology strategist Bob Crepps told an IDF briefing. He outlined three other techniques:

Body bias:­ this varies the voltage of the transistor substrate to reduce leakage, or spurious current flow, when it is not being used but allow faster but leakier operation when it is active.

Stack effect:­ this, paradoxically, uses two transistors instead of one to reduce power. Two light switches in series operate like one if operated at the same time; so will two transistor switches, except their resistance doubles up in the off state, reducing the leakage current.

Sleep transistors: ­ these act like master switches, turning off entire sections of the processor or memory when not required.

A final technique with wider consequences is to have circuits optimised for certain applications. This trend parallels multicore: rather than (or in addition to) packing several general-purpose processors into a chip, you surround the core with modules hardwired to do a particular set of tasks very efficiently. The CSX600 (see opposite) uses a similar principle.

Also in this IDF special:
Intel drive for frugal chips
Viiv PC is built to entertain
Express bus to double speed
UK superchip trounces Xeons
Spat with AMD gets nastier