Shrinking chips hit new bottleneck

Researchers have warned of a new bottleneck in shrinking transistors to produce low-drain chips.

They say the theoretical model engineers use to mitigate the effects of electronic noise in transistors breaks down at nanoscales.

The so-called elastic tunnelling model, which works well at relatively large scales, predicts that the noise frequency will increase as transistors shrink. But research at the US National Institute of Standards and Technology, Maryland College Park University, and Rutgers University shows that the frequencies remains the same, according to a report in EE Times.

The problem, which emerged in studies of the difference between on and off states as transistors are scaled down, shows noise-induced fluctuations get worse as the power decreases."

Lead researcher Jason Campbell told EE Times that it was real bottleneck for low-power transistors. "We have to understand the problem before we can fix it and troublingly we don't know what is actually happening."