Towards 10GHz CPUs

R E L A T E D C O N T E N T

Free email newsletters

The race to 10GHz

Within the next three years processors will be nudging 10GHz, but problems such as power consumption have to be overcome first

Sascha Faber, Personal Computer World 18 Nov 2004

Whether it's processors, graphics chips or memory modules, the semiconductor industry keeps upping the stakes for microchip speed and complexity. But the rapid pace of development is in danger of running into the buffers.

The brakes are on for faster clock speeds due to the problem of heat, because the structures in modern semiconductors are only a few layers of atoms thick. Quantum mechanical effects ensure that current leakage via the thin layers vastly increases and the chips' power consumption and heat loss also see an increase.

Over the past three years the average power consumption of CPUs has almost doubled. In extreme cases, more than 100w are lost in the form of heat, and this figure is increasing.

Providing cooling for the processor is becoming increasingly difficult for component and PC makers. The trick is to use clever technology to get round the problem so that development doesn't grind to a halt and 10GHz processors see the light of day before 2007.

The rule of thumb for semiconductor development is given by Moore's Law: Gordon Moore, Intel's technical director when it was founded, said in 1965 that the complexity of semiconductor chips would double every 18 months and that their computing power would increase correspondingly.

Almost four decades later, this is still the case and is likely to continue to be so for the next 10 years.

The basis of current processor technology is CMOS (Complementary Metal Oxide Semiconductor) transistors. These elements are the simplest components of all modern chips. A transistor has three fundamental components: a source, a drain and a gate.

If a voltage is present at the gate electrode, a current flows from the source to the drain. The path taken by the current is known as the channel. If there is no gate voltage the transistor blocks the flow, functioning as a switch. By utilising this behaviour, multiple transistors can be coupled together to make any electronic circuit.

Six transistors are enough to make a single memory cell in a memory chip. However, the complex functionality of current processors or graphics chips often requires more than 10,000 transistors working together as a single unit.

In total, the number of transistors in a processor can be huge: 106 million on the latest AMD Athlon 64, and 125 million on Intel's Pentium 4, all on a surface the size of a fingernail. Graphics chips are even more complex; Nvidia's Geforce FX 6800 has 222 million transistors.

Ever smaller semiconductor structures are needed to integrate the large number of transistors on a die and to reach higher frequencies. The technical definition of a semiconductor manufacturing process includes the structural size, which is a measure of the smallest size of element used.

The current standard in the PC field is 0.13 micrometres (a micrometre is one millionth of a metre, sometimes referred to by its old name of 'micron'). At the start of 2004 Intel switched to a 90 nanometre (0.09 of a micrometre) manufacturing process for its Prescott Pentium 4 CPUs and AMD followed suit recently.

For comparison, a human hair, at about 100 micrometres, is about a thousand times thicker than the 90-nanometre structures. The influenza virus, at about 100 nanometres, is a similar size.

Even during the switch to 90 nanometre technology, 65 nanometre production is being worked on and 45 nanometre structures are on the semiconductor manufacturers' roadmaps for 2007. By 2011 the emerging standard should be 22 nanometres.

These fine structures are created during chip production in a sequence of photographic, vapour deposition, etching and slicing processes. Hundreds of individual steps and time-consuming processes are necessary before the processor emerges.

If the electricity supply fails and the production process stops ð as was the case after the 1999 Taiwan earthquake ð several weeks' production can be lost.

Layered construction
The starting point for semiconductor manufacture is a thin, polished slice of pure silicon: the wafer. Under strict vacuum conditions layers of different materials, such as silicon dioxide (quartz, SiO2) or doped silicon, are deposited on the wafer.

The structures are created using photo-lithography, where alternate exposure to a light source and etching processes are used to emboss the pattern on the wafer. A photosensitive resist (lacquer) is placed on each layer.

The pattern is then applied by exposing the layer to light through a photo mask, and the areas that were exposed are washed away. Under these exposed areas, the underlying material can be etched away.

Using more and more powerful light sources, it's possible to achieve smaller and smaller circuits. The smallest achievable structure size is directly dependent on the wavelength of the light used, and this reduces with higher photo energy.

Ultraviolet (UV) light, with a wavelength of 193 nanometres, is used in the 90-nanometre process. By making clever use of interference effects, it's possible to generate line widths of 50 nanometres.

Problems arise when the wavelengths become even smaller: at wavelengths of less than 157 nanometres, lenses cannot be used in the optics because neither glass nor crystal is transparent in this range. Instead, mirrors are used, but these are more difficult and expensive to manufacture.

Copper and resistance
Once all the transistors have been built up on the wafer, their contacts must be connected to make the planned circuits. This is done by using metal layers, which are placed above the semiconductor level.

In modern chips, the metal conductors form a complicated three-dimensional interwoven structure of up to nine metal layers, which make up the complex circuitry. Silicon dioxide is used as an insulator between the metal connectors.

For a long time the conductors were made of aluminium, but from 2000 onwards this has gradually been replaced by copper. Using aluminium, because of its low conductivity, caused too much heat loss.

The increased resistance also reduced the rate at which the signal was transmitted. In comparison, copper has the advantage because it is a better conductor, which is also why electrical wires are usually made of copper.

While still on the wafer, the finished semiconductor structures must pass the first tests. During these, the maximum clock speeds are worked out. This decides the speed rating of the chips made from this wafer. Finally, the individual chips are sawn from the wafer and packaged in the processor housing cases.

Cheaper at 300 millimetres
The size of the wafer from which the chips are made has a large influence on production costs. At the moment, most manufacturers are switching from 200mm to 300mm wafers because more than twice as many chips can be made from each wafer.

The total number of chips that can be made from a wafer increases because of the larger area, and at the same time the larger radius of the 300mm wafer means there is less waste at the edges when the rectangular chips are cut out. Using larger wafers also saves up to 40 per cent of the water and electricity used to produce each chip.

Intel already uses 300mm production in four of its fabrication plants (fabs), and is investing $2bn to convert a fifth plant in Arizona by 2005. AMD is equipping its German factory to use 300mm wafers, also by 2005.

New technologies
The new buzzwords as far as production is concerned are silicon-on-insulator (SOI), high-k dielectrics and strained silicon. AMD is combating the unwanted current leakage between source and drain using SOI. This uses an additional insulating oxide layer underneath the source-drain structure to greatly reduce interference caused by leakage currents.

Another problem the processor manufacturers are having to tackle at the moment arises because of the increasingly thin barrier layer between the source-drain channel and the gate electrode.

On Cmos transistors manufactured with the current 90 nanometre technology, the silicon-dioxide layer at 1.2 nanometres is only a few layers of atoms thick and quickly loses its insulating properties. A small current flows through this, which increases power usage.

Help with this should come in the form of special high-dielectric (high-k) materials for the gate layer, that is, layers with a higher dielectric constant. These increase the capacitance and switching speed of the transistor, and at the same time make possible thicker barrier layers of 3.0 nanometres.

Current leakage can be reduced by a factor of 100. Intel plans to use high-k materials in its 45 nanometre manufacturing process by 2007.

Silicon on the rack
Strained silicon technology reduces the transistors' reaction times. An additional silicon-germanium film places the channel area under mechanical tension and distorts the semiconductor material's grid structure. This causes larger inter-atom spacing, so the electrons in the electric current can flow up to 30 per cent faster.

This technology takes advantage of the fact that the grid spacing on the silicon-germanium (SiGe) layer is larger than that for pure silicon, which stretches the lower silicon layers.

While Intel only plans to introduce strained silicon technology in 2005 when its 65-nanometre production starts, AMD plans to introduce it ð together with the SOI method ð at the end of the year when it brings out the 90-nanometre Athlon 64 CPUs.

Transistors in 3D
In the future, both AMD and Intel intend to make use of spatial structures in transistor design: with the trigate transistor the gate layer (unlike in conventional transistors) lies with three sides on the path from the source to the drain.

The larger contact surface makes higher currents and quicker transport possible as well as reducing leakage flows. The introduction of trigate transistors is planned for 2007.

Intel drops the speed tag
Intel's new CPU naming policy gives a clue to whether CPU speeds are likely to go up as expected; the processor speed has vanished from the product description altogether, an indicator that in future, clock speeds might not increase as dramatically as they have in the past.

Despite this, energy-saving options on desktop PCs are becoming more important. AMD has got off to a good start with its Cool & Quiet technology, and Intel is working on similar lines.

There are increasing rumours that Intel is about to merge its desktop and mobile product lines. The developers in Israel are already supposed to be working on Merom, which, from 2007 onwards, should make Intel's mobile CPU technology suitable for use in desktop systems.

In future, improved performance is likely to be delivered not by faster CPUs, but by chips with multiple processor kernels. Intel has already made virtual dual-processor operation possible in the consumer segment with Hyperthreading technology. With AMD's Opteron and Intel's Itanium server CPUs, the first multi-core versions are already officially on the roadmap for 2005.

Going forward
Historically, the semiconductor industry has been able to overcome most of the obstacles thrown in its way. And even though those obstacles are becoming larger and more obstructive, the ingenuity of the researchers shows no signs of abating.

And with so much at stake, it's hardly surprising. The industry doesn't just pay lip service to Moore's Law, it needs to follow it to the letter if the economics of chip production are to remain viable.

Of course, there are absolute physical limits to the size of the features on a piece of silicon, governed by the atomic structure of the silicon itself. But if you think that will stop the march of miniaturisation, you've only got to look at the research that's being done in quantum computing to realise that we're at the dawn of a very exciting era.

See also: